Complex programmable logic devices (CPLDs) are well-known integrated circuits that may be programmed to perform various logic functions. Numerous types of memory elements may be used in CPLD architectures to provide programmability. One such memory element, known as a flash memory cell, is both electrically programmable and erasable. Program and erase are performed on a plurality of flash memory cells using either Fowler-Nordheim tunneling or hot electron injection for programming and Fowler-Nordheim tunneling for erase. Flash memories can also be in-system programmable (ISP). An ISP device can be programmed, erased, and can have its program state verified after it has been connected, such as by soldering, to a system printed circuit board. Some CPLDs do not have ISP capability and must be programmed externally (outside the system) by programming equipment.
Circuit features grow ever smaller with improvements in integrated-circuit process technology. The reduction in feature size improves device performance while at the same time reducing cost and power consumption. Unfortunately, smaller feature sizes also increase a circuit""s vulnerability to over-voltage conditions. Among the more sensitive elements in a modern integrated circuit are the gate oxide layers of the various MOS transistors. In modern devices these layers are very thin, and are consequently easily ruptured by excessive voltage levels. Modern circuits with small feature sizes therefore employ significantly lower source voltages than was common only a few years ago. For example, modern 0.18-micron processes employ supply voltages no greater than 2 volts.
The voltages required to program and erase flash memory cells are dictated by physical properties of the materials used to fabricate memory cells. Unfortunately, these physical properties have not allowed the voltages required to program, erase, and verify the program state of a memory cell to be reduced in proportion to reductions in supply voltages. For example, modern flash memory cells adapted for use with a 0.18-micron processes require program and erase voltages as high as 14 volts, a level far exceeding the required supply voltage. Such memory cells are verified using a range of voltages from about zero volts to about 4.5 volts, the upper end of which is also potentially damaging to sensitive circuits. For a more detailed treatment of program, erase, and verify procedures, see U.S. Pat. No. 5,889,701, which is incorporated herein by reference.
FIG. 1A (prior art) depicts a conventional CPLD 100. CPLD 100 includes a number of input/output (I/O) circuits 105 that may be configured as either input circuits or output circuits by programming appropriate ones of a collection of memory cells 110. Memory cells 110 are depicted in a box for simplicity: they are typically distributed throughout CPLD 100. CPLD 100 includes many additional functional components that are omitted here for brevity. For a more detailed discussion of exemplary CPLDs, see U.S. Pat. No. 6,288,526 and xe2x80x9cCoolRunner(copyright) XPLA3 CPLD, Advance Product Specification,xe2x80x9d DS012 (vl.4), Apr. 11, 2001, both of which are incorporated herein by reference.
I/O circuits 105 are externally accessible via a number of device I/O pins 115. Pins 115 are used both when CPLD 100 is operating as a programmed logic circuit (i.e., is in a logic mode) and during program and verify procedures performed when CPLD 100 is in the test mode. A power line 120 conveys a power-supply voltage VDD from an external supply pin 122 to I/O circuits 105 and the other logic circuits (not shown). CPLD 100 may also include internal voltage generators for developing relatively high voltages to support ISP functionality.
The I/O circuit 105 in the upper left-hand corner of CPLD 120 is shown to include a device input circuit 125 connected to supply line 120. Input circuit 125 has a device input terminal adapted to receive input signals from one of device pins 115 and an output terminal 135 adapted to convey signals to internal logic (not shown). Each I/O circuit 105 also includes an output circuit 130 adapted to convey signals from the internal logic to the respective device pin 115.
During program-state verification, an analog verification signal VFY of between about 0 and 4.5 volts is applied to the control gates of various ones of memory cells 110 via a transmitter circuit 145 and some steering logic 140. As with other designations in the present disclosure, VFY refers to both the verification signal and the corresponding circuit node. Whether a given designation refers to a node or a signal will be clear from the context.
A high-voltage signal HVIN activates transmitter circuit 145 when brought high to pass the verify signal VFY to steering logic 140. As explained below in connection with FIG. 1B, high-voltage signal HVIN is even higher than the maximum verify voltage VFY, and consequently approaches a level that might damage circuitsxe2x80x94such as delicate gate oxidesxe2x80x94internal to input circuit 125. High-voltage signal HVIN is therefore brought onto CPLD 100 via a dedicated pin 121.
FIG. 1B details transmitter circuit 145 of FIG. 1A, including a level shifter 150 and an NMOS output transistor 155. Level shifter 150 shifts a digital control signal CTRL that varies between zero volts and VDD to a similar control signal HV that varies between zero volts and the verify voltage VFY. Control signal CTRL turns off the switched VFY signal VFY_S while steering logic 140 selects the next bit line to which the verify signal VFY will be applied.
Due to the threshold voltage Vth of transistor 155, verify voltage VFY_S will be less than the externally applied verify voltage VFY unless the gate of transistor 155 is brought well above verify voltage VFY. Verify voltage VFY may exceed VDD, and the voltage applied to the gate of transistor 155 must be higher still.
Unfortunately, input circuits 125 in state-of-the-art CPLDs may contain device features too small to accommodate the relatively high voltage HVIN required on device pin 120. For example, if I/O circuits 105 are manufactured using a conventional 0.18-micron process, voltages over about 5 volts can damage input transistors within input circuit 125. The maximum verify voltages VFY required for memory cells 110 in such circuits is approximately 4.5 volts, so verify voltages VFY can be connected to the input terminal of input circuit 125 as shown; however, the threshold voltage required to pass a 4.5 volt signal through transistor 145 without substantial degradation will be approximately 6 or 7 volts. A dedicated device pin 120 is therefore provided to convey this relatively high voltage HUIN.
Integrated circuits are becoming ever more densely populated as processing technology improves. As circuit features grow smaller, the number of physical pads that fit on the die surface becomes a limiting factor on the amount of logic instantiated on a circuit die. Due to the pad-limited nature of modern devices, device pins are at a premium. It is therefore undesirable to provide a dedicated pin 120 for the purposes of test at the expense of a general purpose I/O circuit 105.
A CPLD in accordance with the invention employs a low-voltage, non-degenerative transmitter circuit to eliminate the need for a dedicated control pin to provide the relatively high voltage levels required to verify the program states of programmable memory cells. Eliminating the need for a dedicated control pin frees up valuable chip real estate for the inclusion of an additional general-purpose input/output pin.
The appended claims, and not this summary, define the scope of the invention.